1. Technical Field
The present invention relates to a field effect transistor with a heterostructure and to an associated production method, and in particular to a sub-100 nm field effect transistor with a fully depleted active region.
2. Background Information
As the development of semiconductor components, and in particular field effect transistors, advances, ever shrinking feature sizes are striven for in order to improve an integration density and switching speed. However, specific limits are encountered in this case on account of a limited charge carrier mobility in semiconductor materials. Since an upper limit of the charge carrier mobility of electrons and holes in a semiconductor crystal depends on the physical properties of the semiconductor crystal, the switching speed of the field effect transistors is inherently limited by the semiconductor crystal. Furthermore, so-called high-k gate dielectrics (that is to say dielectrics having a high dielectric constant) that are necessary for the rising integration density also cause a reduced charge carrier mobility.
Therefore, so-called field effect transistors with stress-absorbing or strained semiconductor layers have been developed, whereby it is possible to improve a charge carrier mobility in a strained semiconductor crystal.
In modern logic chips, such as, for example, microcontrollers, microprocessors, telecommunications chips, etc., a significant requirement furthermore consists in being able to set the threshold voltage (Vt) of the field effect transistors (n/p-MOS) highly precisely in a manner adapted to a respective application. In the case of conventional, for example CMOS, field effect transistors with their n+/p+-polycrystalline gate electrodes, said threshold voltage is usually set by way of the substrate doping. In the case of the fully depleted semiconductor structures or “fully depleted silicon on insulator” structures discussed below, however, it is no longer possible to adopt the usual manner of setting said threshold voltage of the field effect transistors by way of a substrate doping, since the statistical variation of the dopants in the small active volume would lead to extremely severe fluctuations in the threshold voltage that are unacceptable to circuit designers. Furthermore, it is also no longer possible to use n/p doped polysilicon as the gate electrode, since these materials lead to extremely low threshold voltages and are thus unsuitable for future logic components.
One method for eliminating these problems is to set the threshold voltage of a field effect transistor by varying the gate capacitance. This exploits the circumstance that the threshold voltage of the field effect transistor increases as the gate capacitance decreases.
A further method for setting a threshold voltage of field effect transistors conventionally consisted in suitably altering the so-called flat band voltage, which essentially depends on the difference between the work functions of the gate electrode and the substrate material. For an undoped FD-SOI structure (fully depleted silicon on insulator), by way of example, a gate electrode made of metal having a work function of 4.7 eV leads to symmetrical threshold voltages for the n and p MOS field effect transistors. However, this approach leads to very high threshold voltages of approximately 500 mV for n- and p-MOS field effect transistors and is therefore not suitable for future logic components. Conventional methods and field effect transistors of this type cannot be used in particular for so-called ASICs (application specific integrated circuit) or microprocessors for which a threshold voltage of the field effect transistors of at most 350 mV is necessary.
In principle, it could furthermore be attempted to alter the work function of the gate electrodes for example by means of implanting suitable dopants or by using different metals or metal alloys in such a way as to produce a suitable or sufficiently small threshold voltage. However, extremely great difficulties arise here in terms of actually finding the exactly correct materials and integrating them in a CMOS process. In particular the requirements made of a symmetrical threshold voltage in a CMOS circuit for both n and p MOS field effect transistors lead to extremely cost-intensive solutions.